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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SHARC FAMILY CORE ARCHITECTURE
The ADSP-2136x is code-compatible at the assembly level with
the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the
first generation ADSP-2106x SHARC processors. The
ADSP-2136x shares architectural features with the ADSP-2126x
and ADSP-2116x SIMD SHARC processors, as shown in
Figure 2 and detailed in the following sections.
SIMD Computational Engine
The processor contains two computational processing elements
that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY can be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele-
ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive signal
processing algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements.
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or
the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing
elements. These computation units support IEEE 32-bit,
single-precision floating-point, 40-bit extended-precision
floating-point, and 32-bit fixed-point data formats.
S
SIMD Core
JTAG
FLAG
TIMER INTERRUPT CACHE
PM ADDRESS 24
DMD/PMD 64
5 STAGE
PROGRAM SEQUENCER
PM DATA 48
DAG1
16x32
DAG2
16x32
PM ADDRESS 32
SYSTEM
DM ADDRESS 32
PM DATA 64
DM DATA 64
I/F
USTAT
4x32-BIT
PX
64-BIT
RF
DATA
RF
MULTIPLIER
SHIFTER
ALU
Rx/Fx
PEx
SWAP
Sx/SFx
PEy
ALU
SHIFTER
MULTIPLIER
16x40-BIT
16x40-BIT
MRF
MRB
MSB
MSF
80-BIT
80-BIT
ASTATx
ASTATy
80-BIT
80-BIT
STYKx
STYKy
Figure 2. SHARC Core Block Diagram
Rev. J |
Page 4 of 60 |
July 2013
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